Method for semiconductor die edge protection and semiconductor die separation

ABSTRACT

Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. application Ser. No.16/923,754, filed Jul. 8, 2020, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

The present disclosure generally relates to semiconductor dieassemblies, and more particularly relates to semiconductor die edgeprotection and semiconductor die separation.

BACKGROUND

Semiconductor packages typically include one or more semiconductor dies(e.g., memory chip, microprocessor chip, imager chip) mounted on asubstrate, encased in a protective covering. The semiconductor dies mayinclude functional features, such as memory cells, processor circuits,or imager devices, as well as bond pads electrically connected to thefunctional features. The bond pads can be electrically connected tocorresponding conductive structures of the substrate, which may becoupled to terminals outside the protective covering such that thesemiconductor die can be connected to higher level circuitry.

In some semiconductor packages, two or more semiconductor dies may bestacked on top of each other to reduce footprints of the semiconductorpackages (which may be referred to as multi-chip packages). The stackedsemiconductor dies may include three-dimensional interconnects (e.g.,through-silicon vias (TSVs)) to route electrical signals between thesemiconductor dies. The semiconductor dies may be thinned to reduceoverall thicknesses of such semiconductor packages, as well as tomitigate issues related to forming the three-dimensional interconnectsthrough the stacked semiconductor dies. Typically, a carrier wafer isattached to a front side of a substrate (e.g., a wafer) having thesemiconductor dies fabricated thereon such that the substrate may bethinned from its back side. Further, the substrate may be diced tosingulate individual semiconductor dies while attached to an adhesivelayer of a sheet of mount tape. The dicing step, however, tends togenerate particles that causes yield loss. Further, the dicing steputilizing a blade may be incompatible with new advanced materialsincluded in the semiconductor dies.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present technology can be better understood withreference to the following drawings. The components in the drawings arenot necessarily to scale. Instead, emphasis is placed on illustratingclearly the principles of the present technology and overall features.

FIGS. 1A through 1L illustrate an example process of protectingsemiconductor die edge and separating semiconductor dies in accordancewith an embodiment of the present technology.

FIGS. 2 and 3 are flowcharts illustrating methods of protectingsemiconductor die edge and separating semiconductor dies in accordancewith embodiments of the present technology.

DETAILED DESCRIPTION

Specific details of several embodiments for protecting edges (and/orback sides) of semiconductor dies and separating the semiconductor diesfor semiconductor device assemblies, and associated methods aredescribed below. The scheme of protecting edges of semiconductor dies asdescribed herein may not only provide for a passivation layer aroundedges (and a back side) of a semiconductor die but also provide analternative die separation technique suitable for integrating newmaterials and/or deploying advanced packaging technology compared toconventional dicing techniques. For example, the passivation layeraround the edges of semiconductor dies may reduce cracks (or chipping)at the edges or propagation of such cracks inward toward integratedcircuits and/or various components of the semiconductor dies.Additionally, the passivation layer may include a diffusion barrier(e.g., a nitride layer) to block contaminants (e.g., metallic atoms suchas copper) from diffusing through silicon substrate of the semiconductordie, which may cause certain reliability issues.

Moreover, the die separation technique in accordance with the presenttechnology may eliminate conventional dicing steps (e.g., blade dicing,laser dicing) that generate particles that attach to the surface of thedies, causing yield loss. The conventional dicing steps also presentschallenges for integrating new materials (e.g., low-k and/or extremelow-k materials) that may be used to build state-of-the-artsemiconductor devices. In some cases, the conventional dicing steps mayleave contaminants on the surface of the semiconductor dies, which, inreturn, may hinder deploying advanced packaging techniques—e.g., acombination bonding technique that forms direct bonding of twosemiconductor dies, face-to-face.

As such, the scheme of protecting edges of semiconductor dies andseparating semiconductor dies in accordance with the present technologyprovides various benefits, such as decreasing particle counts to improveyield, protecting the semiconductor dies to improve reliability,reducing contaminants for deploying advanced packaging techniques,facilitating integration of new materials that may be incompatible withconventional dicing technique, among others. Further, the presenttechnology may reduce width of dicing lanes such that more semiconductordies may be generated per wafer—e.g., reducing a production cost. Asdescribed in more detail below, the present technology may facilitaterelieving wafer-level mechanical stress during the wafer back sideprocessing steps (e.g., reduced wafer warpage) due to an adhesivematerial placed between semiconductor dies, which may absorb stressesexerted on the wafer.

The term “semiconductor device or die” generally refers to a solid-statedevice that includes one or more semiconductor materials. Examples ofsemiconductor devices include logic devices, memory devices,microprocessors, or diodes, among others. Such semiconductor devices mayinclude integrated circuits or components, data storage elements,processing components, and/or other features manufactured onsemiconductor substrates. Further, the term “semiconductor device ordie” can refer to a finished device or to an assembly or other structureat various stages of processing before becoming a finished device.Depending upon the context in which it is used, the term “substrate” canrefer to a wafer-level substrate or to a singulated, die-levelsubstrate. Also, a substrate may include a semiconductor wafer, apackage support substrate, an interposer, a semiconductor device or die,or the like. A person having ordinary skill in the relevant art willrecognize that suitable steps of the methods described herein can beperformed at the wafer level or at the die level.

Further, unless the context indicates otherwise, structures disclosedherein can be formed using conventional semiconductor-manufacturingtechniques. Materials can be deposited, for example, using chemicalvapor deposition (CVD), physical vapor deposition (PVD), atomic layerdeposition (ALD), spin coating, plating, and/or other suitabletechniques. Similarly, materials can be removed, for example, usingplasma etching, wet etching, chemical-mechanical planarization (CMP), orother suitable techniques. Some of the techniques may be combined withphotolithography processes. A person skilled in the relevant art willalso understand that the technology may have additional embodiments, andthat the technology may be practiced without several of the details ofthe embodiments described herein with reference to FIGS. 1A-1L, 2, and 3.

As used herein, the terms “front,” “back,” “vertical,” “lateral,”“down,” “up,” “upper,” and “lower” can refer to relative directions orpositions of features in the semiconductor device assemblies in view ofthe orientation shown in the Figures. For example, “upper” or“uppermost” can refer to a feature positioned closer to the top of apage than another feature. These terms, however, should be construedbroadly to include semiconductor devices having other orientations. Aperson skilled in the relevant art will also understand that thetechnology may have additional embodiments, and that the technology maybe practiced without several of the details of the embodiments describedherein with reference to FIGS. 1A-1L, 2, and 3 .

FIG. 1A illustrates a cross-sectional diagram of a substrate 105 thatincludes semiconductor dies 115 (e.g., semiconductor dies 115 a through115 c) fabricated on its front side 106. Each semiconductor die 115 mayinclude an integrated circuit formed on its front side. Further, thesemiconductor die 115 may include one or more vias (depicted in FIGS.1G, 1H, 1I, and 1L) coupled with the integrated circuit, and extendingfrom the front side to a back side of the semiconductor die 115. The oneor more vias (which may also be referred to as through-silicon vias(TSVs)) are configured to provide one or more electrical connections forthe integrated circuit on the back side—e.g., to facilitate stacking ofmultiple semiconductor die 115 on top of each other. The integratedcircuit and the vias of the semiconductor die 115 are omitted whenmultiple semiconductor dies 115 are depicted in FIGS. 1A-1L in arelatively low magnification for clear illustration of certain aspectsof the principles of the present technology.

FIG. 1A also depicts a set of trenches 120 (e.g., trenches 120 a through120 c) formed on the front side 106, as well as a photo resist layer 110used to protect the semiconductor dies 115. As such, individual trenches120 may correspond to scribe lines (or dicing lanes) of the substrate105. In some embodiments, the photo resist layer 110 can include a hardmask layer (e.g., a hard mask with carbon). In some embodiments, formingthe trenches 120 may be accomplished by performing an etch process(e.g., plasma-based dry etch process, wet etch process) known to aperson skilled in the art of semiconductor fabrication technology.Although the trenches 120 are depicted to include vertical sidewalls, insome embodiments, the sidewalls of the trenches 120 may be sloped. Forexample, openings of the trenches 120 may be greater at the surface ofthe substrate 105 than those at the bottom of the trenches 120—e.g.,sidewalls with a positive slope. The positive slope of the sidewalls mayfacilitate formation of a dielectric layer (e.g., the first dielectriclayer 125) on the sidewalls to be more uniform, in some cases.

Dimensions of the trenches 120 include a width (denoted as “W” in FIG.1A) and a depth D (denoted as “D” in FIG. 1A). The width of the trenches120 may be less than typical widths of a dicing lane (a scribe line),which may be approximately 60 to 80 μm wide (e.g., within 10% of 60 μm,within 10% of 80 μm). In some embodiments, the width of trenches 120 maybe approximately 40 μm (e.g., within 10% of 40 μm), 30 μm (e.g., within10% of 30 μm), or even less. Further, the depth of trenches 120 can bedetermined based on a final thickness of the semiconductor dies 115(denoted as “T” in FIG. 1G). Namely, the depth of trenches 120 may bedevised to be greater than the final thickness of the semiconductor dies115 such that individual semiconductor dies 115 can be singulatedwithout a dicing process. For example, when the final thickness of thesemiconductor dies 115 is approximately 50 μm (e.g., within 10% of 50μm), the depth of trenches 120 may be approximately 55 to 60 μm (e.g.,within 10% of 55 μm, within 10% of 60 μm). Additionally, oralternatively, the width and depth of the trenches 120 may be based onthe aspect ratio determined by the width and depth of the trenches 120,considering the process capability associated with downstream processsteps, such as process steps forming a dielectric layer (e.g., achemical vapor deposition (CVD) process, a physical vapor deposition(PVD) process) on the sidewalls of the trenches 120 and/or filling thetrenches 120 with an adhesive material, among others.

FIG. 1B illustrates a cross-sectional diagram of the substrate 105,after the photo resist layer 110 has been removed, and subsequently, afirst dielectric layer 125 has been formed on the front side 106 of thesubstrate 105. The first dielectric layer 125 can be formed byperforming one or more process steps, including a CVD process, forexample. The first dielectric layer 125 may include various dielectricmaterials, such as an oxide, a nitride, an oxynitride, or a combinationthereof. In some embodiments, an oxide layer may be formed on thesilicon surface, followed by a nitride layer deposited on the oxidelayer formed on the silicon surface. Such a composite layer may reduceformation of defects (e.g., crystalline defects in the substrate 105)when compared to a single layer of nitride directly formed on thesilicon surface.

FIG. 1C illustrates a cross-sectional diagram of the substrate 105,after the first dielectric layer 125 has been removed from the frontside 106 of the substrate 105, and from the bottom of the individualtrenches 120. As a result, the first dielectric layer 125 remains on thesidewalls of the trenches 120. In some embodiments, an etch process(e.g., plasma-based dry etch process) may be performed to remove thefirst dielectric layer 125 from relatively flat regions (e.g., the frontside 106, the bottom of the trenches 120) with respect to incoming fluxof etchants, while retaining the first dielectric layer 125 on thesidewalls.

FIG. 1D illustrates a cross-sectional diagram of the substrate 105,after the trenches 120 (with the first dielectric layer 125 formed ontheir sidewalls) has been filled with an adhesive material 130—e.g.,Nissan Chemical thermoset adhesive. The adhesive material 130 (which maybe referred to as carrier adhesive) also covers (e.g., coats) the frontside 106 of the substrate 105. The sidewalls of the trenches 120 areprotected by the first dielectric layer 125 to prevent the adhesivematerial 130 directly contacting the sidewalls. In some embodiments, theadhesive material 130 may exhibit a fluid-like material property suchthat the trenches 120 with a high aspect ratio (e.g., a relativelynarrow opening with a relatively deep trench bottom) can be filled.Further, the substrate 105 in FIG. 1D has been flipped to depict theback side 107 above the front side 106.

FIG. 1E illustrates a cross-sectional diagram of the substrate 105,after a carrier substrate 135 (or a support substrate) has been bondedusing the adhesive material 130 on the front side 106. The carriersubstrate 135 may mechanically support the substrate 105 (and thesemiconductor dies 115) during subsequent process steps to be performedon the back side 107—e.g., process steps described with reference toFIGS. 1F through 1J. Further, the adhesive material 130 can be densified(e.g., set, cured) such that the adhesive material 130 becomes suitablefor the subsequent processing steps. In some embodiments, a thermalprocess may be applied to the adhesive material 130 (e.g., thermallysetting the adhesive material 130). Additionally, or alternatively, achemical process may be applied to the adhesive material 130 (e.g.,chemically setting the adhesive material 130).

FIG. 1F illustrates a cross-sectional diagram of the substrate 105,after a first portion of the substrate 105 has been removed from theback side 107 of the substrate 105 (as indicated with arrows). In someembodiments, a backgrind and/or a chemical mechanical polishing (CMP)process (e.g., a first process) may be performed to remove the bulk ofthe substrate 105—e.g., thinning the substrate 105 from approximately700 μm (e.g., within 10% of 700 μm) to approximately 100 μm (e.g.,within 10% of 100 μm) or less. In other embodiments, a different process(e.g., an etch process) may be performed to remove the bulk of thesubstrate 105, which a person skilled in the art of semiconductorfabrication may be familiar with.

FIG. 1G illustrates a cross-sectional diagram of the substrate 105,after a second portion of the substrate 105 has been removed from theback side 107 of the substrate 105. In some embodiments, an etch process(e.g., a second process) may be performed to the back side 107 after thebulk of the substrate 105 has been removed (e.g., using the CMP processdescribed with reference to FIG. 1F). The etch process may be configuredto expose the adhesive material 130 in the trenches 120 from the backside 107 as a result of removing the second portion of the substrate105. Further, the etch process may be devised to expose one or morethrough-silicon vias (TSVs) 140 of the semiconductor dies 115 from theback side 107. The TSVs are coupled with an integrated circuit 141formed on the front side 106 of the substrate 105, and configured toprovide one or more electrical connections for the integrated circuit141 on the back side 107. In some embodiments, the back side 107 of thesubstrate 105 may be recessed with respect to the exposed adhesivematerial 130 after removing the second portion of the substrate 105. Assuch, the second process (e.g., the etch process) may be configured toremove the semiconductor substrate 105 at a first removal rate and theadhesive material 130 (and/or the first dielectric layer 125) at asecond removal rate that is less than the first removal rate.

It should be appreciated that, after completing the second process toexpose the adhesive material 130 in the trenches 120 from the back side107 (e.g., when the etch front proceeds past the bottom of trenches 120from the back side 107), the semiconductor dies 115 are separated fromthe substrate 105 because the depth of the trenches 120 is determined tobe greater than the final thickness of the semiconductor dies 115 (e.g.,the thickness of the semiconductor dies 115 at the completion of theetch process). In other words, individual semiconductor dies 115 areseparated from the substrate 105 because the portion of the substrate105 common to all semiconductor dies 115 no longer exist as a result ofcompleting the second process (e.g., the etch process). Thereafter,individual semiconductor dies 115 are held to each other and to thecarrier substrate 135 by the adhesive material 130. In this manner, acombination of forming trenches 120 on the front side 106 of thesubstrate 105 and thinning the substrate 105 from the back side 107 pastthe bottom of the trenches 120 accomplishes separating the semiconductordies 115 from the substrate 105, thereby eliminating dicing steps thatphysically sever the semiconductor dies 115 from the substrate 105.

Still referring to FIG. 1G, as the substrate 105 common to thesemiconductor dies 115 no longer exists and the semiconductor dies 115are coupled with each other by the adhesive material 130, a warpage ofthe substrate 105 may be avoided during the subsequent process steps tobe performed on the back side 107 of the semiconductor dies 115. Inother words, pressure (or force) that may be exerted on thesemiconductor dies 115 through the wafer back side processing steps maybe at least partially absorbed by the adhesive material 130 in lieu ofsubjecting the substrate 105 to the pressure (or force) that maygenerate defects (e.g., slippage, crystalline dislocations) in thesubstrate 105—e.g., during de-bonding step.

As described herein, various process steps associated with formingtrenches 120 filled with the adhesive material 130 (and the firstdielectric layer 125) and thinning the substrate 105 from the back side107 of the substrate 105 include conventional semiconductor processsteps that may be performed in semiconductor fabrication environments(e.g., a clean room environment). The clean room process steps areinherently cleaner than a conventional dicing process involvingmechanical dicing of the substrate 105. Thus, the semiconductor dies 115separated from the substrate 105 in accordance with the presenttechnology may benefit from the clean room process steps, such asreduced particles, debris, contaminants, damages, cracks, or the like,to improve yield and reliability of the semiconductor dies 115.Moreover, the final thickness of the semiconductor dies 115 may bethinner than that of the semiconductor dies 115 separated by theconventional dicing process—e.g., the semiconductor dies 115 may nothave to maintain a certain thickness to sustain various forces duringthe dicing process. Thinner semiconductor dies 115 may reduce packageheights and/or facilitate utilizing an advanced packaging technique(e.g., combination bonding) for the semiconductor dies 115.

Further, when compared with a dicing technique, the clean room processsteps may be more compatible with integrating new materials (e.g., low-kdielectric material, extreme low-k dielectric material) that may beessential for advanced semiconductor devices. Additionally, the presenttechnology may reduce a production cost of the semiconductor dies 115because of the nature of wafer level processes that concurrentlyseparates all the semiconductor dies 115 from the substrate 105, insteadof having a saw cutting a row (or a column) of semiconductor dies 115,one row (or column) at a time. Other benefits of the present technologymay include a flexible placement of the semiconductor dies 115 on thesubstrate 105 (which may be referred to as a wafer map of semiconductordies) to increase a total quantity of semiconductor dies as the trenches120 are not required to form straight lines (as in dicing lanes). Forexample, one or more rows (or columns) of semiconductor dies 115 may beshifted with respect to neighboring rows (or columns) of semiconductordies 115 such that a quantity of partial dies around the perimeter ofthe wafer may be reduced. Moreover, the present technology mayfacilitate variations in shapes and sizes of the semiconductor dies 115within a semiconductor wafer. For example, individual semiconductor dies115 may be in a hexagonal shape (or different shapes other thanconventional rectangular shape)—e.g., the hexagonal shape may increase atotal quantity of memory dies that can be placed in a semiconductorwafer or provide an efficient layout of various components within thesemiconductor die.

FIG. 1H illustrates a cross-sectional diagram of the semiconductor dies115 attached to the carrier substrate 135, after a second dielectriclayer 145 has been formed on the back side 107. The second dielectriclayer 145 can be formed by performing one or more process steps, such asdeposition processes (e.g., CVD and/or PVD processes) described withreference to FIG. 1B. The second dielectric layer 145 may includevarious dielectric materials, such as an oxide, a nitride, anoxynitride, or a combination thereof. In some example embodiments, thesecond dielectric layer 145 may include a composite layer having anitride and an oxide formed at a relatively low temperature (which maybe referred to as low temperature nitride and oxide (LTNO)). In otherexample embodiments, the second dielectric layer 145 may include asilicon nitride (SiN) layer and/or a layer of tetraethyl orthosilicate(TEOS). The second dielectric layer 145 may protect the back side 107 ofindividual semiconductor dies 115 from contaminants (e.g., copper)and/or during subsequent processing steps—e.g., one or more cleaningsteps to remove the adhesive material 130, forming conductive components(e.g., under-bump metallization (UBM) structures for the TSVs 140).After forming the second dielectric layer 145, the TSVs 140 may beburied within the second dielectric layer 145. Further, an interface 150may form between the second dielectric layer 145 and the firstdielectric layer 125 (and/or the adhesive material 130).

FIG. 1I illustrates a cross-sectional diagram of the semiconductor dies115 attached to the carrier substrate 135, after a portion of the seconddielectric layer 145 has been removed to expose the TSVs 140 of thesemiconductor dies 115 from the back side 107. In some embodiments, aCMP process may be performed to remove the portion of the seconddielectric layer 145 to expose the TSVs 140 of the semiconductor dies115. In other embodiments, an etch process may be performed to removethe portion of the second dielectric layer 145 to expose the TSVs 140 ofthe semiconductor dies 115. The interface 150 between the firstdielectric layer 125 and the second dielectric layer 145 may remainafter the CMP process step (or the etch process step).

In some embodiments, after exposing the TSVs 140 on the surface of thesecond dielectric layer 145, one or more process steps may be performedon the back side 107 to form conductive components—e.g., UBM structurescorresponding to the TSVs 140 to facilitate stacking of thesemiconductor dies 115. Such process steps may include additionaldeposition process steps (e.g., forming one or more metallic/conductivelayers), photolithography process steps (e.g., defining UBM structurescorresponding to the TSVs 140), etch process steps (e.g., removingexcessive metallic/conductive materials where unnecessary), cleanprocess steps (e.g., removing photo resists, removing variousby-products generated during etch process steps), among others. Theadhesive material 130, once cured (e.g., thermally set as described withreference to FIG. 1E), may exhibit material properties (e.g., modulus ofrigidity) sufficient to sustain its structural and/or compositionalintegrity during the process steps—e.g., remaining within the trenches120. The adhesive material 130, however, may be removed using a specificsolvent that selectively dissolves the adhesive material 130.

FIG. 1J illustrates a cross-sectional diagram of the semiconductor dies115 attached to the carrier substrate 135, after the adhesive material130 within the trenches 120 has been partially removed from the backside 107 using a cleaning process (e.g., using the specific solvent thatdissolves the adhesive material 130). Removing the portion of theadhesive material 130 at this stage facilitates completely removing theadhesive material 130 from the trenches 120 as described with referenceto FIG. 1L. In some embodiments, this cleaning step may be omitted.

FIG. 1K illustrates a cross-sectional diagram of the semiconductor dies115 attached to a sheet of film frame 155, after the carrier substrate135 has been detached (de-bonded) from the semiconductor dies 115 (e.g.,by removing the adhesive material 130 between the carrier substrate 135and the semiconductor dies 115). Further, the semiconductor dies 115 inFIG. 1K has been flipped to depict the front side 106 above the backside 107. FIG. 1K also depicts remaining adhesive material 130 withinthe trenches 120.

FIG. 1L illustrates a cross-sectional diagram of the semiconductor dies115 attached to the sheet of film frame 155, after the adhesive material130 in the trenches 120 has been removed. Subsequently, individual dies115 may be tested for their functionality and picked up from the sheetof film frame 155 for further processing, e.g., stacking multiplesemiconductor dies 115 to form a semiconductor die assembly.

Each semiconductor die 115 may include an integrated circuit (e.g., theintegrated circuit 141) formed on a front side (e.g., the front side106) of a semiconductor substrate, a first dielectric layer (e.g., thefirst dielectric layer 125) on a sidewall of the semiconductorsubstrate, and a second dielectric layer (e.g., the second dielectriclayer 145) on a back side (e.g., the back side 107) of the semiconductorsubstrate opposite to the front side, where the second dielectric layermay be discontinuous from the first dielectric layer (e.g., due to theinterface 150 between the first dielectric layer 125 and the seconddielectric layer 145). In some embodiments, the first dielectric layerincludes at least two dielectric materials—e.g., an oxide layer incontact with the sidewall of the semiconductor substrate and a nitridelayer in contact with the oxide layer. In some embodiments, the firstdielectric layer includes a first dielectric material (e.g., oxide), andthe second dielectric layer includes a second dielectric material (e.g.,nitride) different from the first dielectric material. In someembodiments, the first and second dielectric materials include an oxide,a nitride, an oxynitride, or a combination thereof. In some embodiments,the semiconductor die 115 may include one or more vias (e.g., TSVs 140)extending from the front side of the semiconductor substrate past thesecond dielectric material on the back side, where the one or more viasare coupled with the integrated circuit and configured to provide one ormore electrical connections for the integrated circuit on a surface ofthe second dielectric material (e.g., the second dielectric layer 145).

FIG. 2 is a flowchart 200 illustrating a method of protecting edges ofsemiconductor dies in accordance with an embodiment of the presenttechnology. The flowchart 200 may include aspects of methods asdescribed with reference to FIGS. 1A through 1L.

The method includes forming a plurality of trenches on a front side of asubstrate including a plurality of semiconductor dies, where individualtrenches of the plurality correspond to scribe lines of the substrate(box 210). The method further includes filling each of the plurality oftrenches with an adhesive material (box 215). The method furtherincludes thinning the substrate from a back side of the substrate (box220). The method further includes removing the adhesive material tosingulate individual semiconductor dies of the plurality (box 225).

In some embodiments, forming the plurality of trenches includesperforming an etch process on the front side of the substrate. In someembodiments, each trench of the plurality of trenches includes a depthgreater than a thickness of the singulated individual semiconductordies. In some embodiments, the method may further include forming afirst dielectric layer on sidewalls of the plurality of trenches, priorto filling each of the plurality of trenches with the adhesive material.In some embodiments, the method may further include attaching, prior tothinning the substrate from the back side, a carrier substrate to thesubstrate using the adhesive material on the front side of thesubstrate.

In some embodiments, thinning the substrate from the back side includesexposing the adhesive material in each of the plurality of trenches fromthe back side of the substrate. In some embodiments, the method mayfurther include forming, after thinning the substrate from the backside, a second dielectric layer on the back side of the substrate, andremoving at least a portion of the second dielectric layer to expose theadhesive material in each of the plurality of trenches. In someembodiments, removing at least the portion of the second dielectriclayer also exposes one or more through-silicon vias (TSVs) of theplurality of semiconductor dies. In some embodiments, the method mayfurther include attaching a sheet of film frame to the second dielectriclayer remaining on the back side of the substrate, prior to removing theadhesive material.

FIG. 3 is a flowchart 300 illustrating a method of protecting edges ofsemiconductor dies in accordance with an embodiment of the presenttechnology. The flowchart 300 may include aspects of methods asdescribed with reference to FIGS. 1A through 1L.

The method includes forming a plurality of trenches on a front side of asemiconductor substrate including a plurality of semiconductor dies,each trench of the plurality of trenches having a depth greater than afinal thickness of individual semiconductor dies (box 310). The methodfurther includes forming a first dielectric layer on sidewalls of theplurality of trenches (box 315). The method further includes fillingeach of the plurality of trenches with an adhesive material that coatsthe front side of the semiconductor substrate (box 320). The methodfurther includes thinning the semiconductor substrate from a back sideof the semiconductor substrate to the final thickness (box 325). Themethod further includes removing the adhesive material to singulateindividual semiconductor dies (box 330).

In some embodiments, forming the first dielectric layer on the sidewallsfurther comprises forming the first dielectric layer on the front sideof the semiconductor substrate including the plurality of trenches, andperforming an etch process on the front side of the semiconductorsubstrate to remove the first dielectric layer from the front side ofthe semiconductor substrate and from the bottom of individual trenchesof the plurality. In some embodiments, the method may further compriseattaching, prior to thinning the semiconductor substrate, a carriersubstrate to the semiconductor substrate using the adhesive material onthe front side of the semiconductor substrate.

In some embodiments, thinning the semiconductor substrate from the backside further comprises removing a first portion of the semiconductorsubstrate from the back side using a first process without exposing theadhesive material in the trenches, and removing, after removing thefirst portion, a second portion of the semiconductor substrate from theback side using a second process to expose the adhesive material in thetrenches as a result of removing the second portion of the semiconductorsubstrate. In some embodiments, the second process is configured toremove the semiconductor substrate at a first removal rate and theadhesive material at a second removal rate less than the first removalrate. In some embodiments, the back side of the semiconductor substrateis recessed with respect to the exposed adhesive material after removingthe second portion.

It should be noted that the methods described above describe possibleimplementations, and that the operations and the steps may be rearrangedor otherwise modified and that other implementations are possible.Furthermore, embodiments from two or more of the methods may becombined.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. For example, although the foregoing example process sequenceillustrates the first process (e.g., the CMP process) achieving theresults depicted in FIG. 1F and the second process (e.g., the etchprocess) achieving the results depicted in FIG. 1G as two separateprocess steps utilizing two different process modules (e.g., CMP moduleand etch module), the present technology is not limited thereto. Namely,process steps to thin the substrate 105 to expose the adhesive material130 (and the TSVs 140) from the back side 107 may be performed withoutusing two different process modules.

For example, after removing the bulk of the substrate 105 using the CMPprocess to achieve the results depicted in FIG. 1F (e.g., based on atotal CMP process time using a previously established substrate removalrate), various process parameters for the CMP process may be modified(e.g., using a different slurry, changing pressures associated with awafer chuck and/or a stage of the CMP tool, tweaking rotationspeeds/directions of the wafer chuck and/or the stage, etc.) to reducethe substrate removal rate such that the CMP process may continue toremove the substrate 105 with a fine-tuned removal rate to expose theadhesive material 130 to achieve the results depicted in FIG. 1G,thereby without switching to an etch process. Additionally, oralternatively, the CMP process may utilize an endpoint mechanism basedon detecting a change in friction monitored by a motor of the CMP toolwhen the first dielectric layer 125 and the adhesive material 130 isexposed. Such an endpoint mechanism may indicate that the CMP processhas reached to the bottom of trenches 120 from the back side 107, atleast in certain areas of the substrate 105 such that the CMP processcan be fine-tuned thereafter to precisely control the removal rate. Inaddition, certain aspects of the present technology described in thecontext of particular embodiments may also be combined or eliminated inother embodiments.

The devices discussed herein, including a semiconductor device, may beformed on a semiconductor substrate or die, such as silicon, germanium,silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In somecases, the substrate is a semiconductor wafer. In other cases, thesubstrate may be a silicon-on-insulator (SOI) substrate, such assilicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layersof semiconductor materials on another substrate. The conductivity of thesubstrate, or sub-regions of the substrate, may be controlled throughdoping using various chemical species including, but not limited to,phosphorous, boron, or arsenic. Doping may be performed during theinitial formation or growth of the substrate, by ion-implantation, or byany other doping means.

As used herein, including in the claims, “or” as used in a list of items(for example, a list of items prefaced by a phrase such as “at least oneof” or “one or more of”) indicates an inclusive list such that, forexample, a list of at least one of A, B, or C means A or B or C or AB orAC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase“based on” shall not be construed as a reference to a closed set ofconditions. For example, an exemplary step that is described as “basedon condition A” may be based on both a condition A and a condition Bwithout departing from the scope of the present disclosure. In otherwords, as used herein, the phrase “based on” shall be construed in thesame manner as the phrase “based at least in part on.”

From the foregoing, it will be appreciated that specific embodiments ofthe invention have been described herein for purposes of illustration,but that various modifications may be made without deviating from thescope of the invention. Rather, in the foregoing description, numerousspecific details are discussed to provide a thorough and enablingdescription for embodiments of the present technology. One skilled inthe relevant art, however, will recognize that the disclosure can bepracticed without one or more of the specific details. In otherinstances, well-known structures or operations often associated withmemory systems and devices are not shown, or are not described indetail, to avoid obscuring other aspects of the technology. In general,it should be understood that various other devices, systems, and methodsin addition to those specific embodiments disclosed herein may be withinthe scope of the present technology.

What is claimed is:
 1. A semiconductor device, comprising: an integratedcircuit formed on a front side of a semiconductor substrate; a firstdielectric layer on a sidewall of the semiconductor substrate; and asecond dielectric layer on a back side of the semiconductor substrateopposite to the front side, the second dielectric layer discontinuousfrom the first dielectric layer.
 2. The semiconductor device of claim 1,wherein the first dielectric layer includes at least two dielectricmaterials.
 3. The semiconductor device of claim 1, wherein: the firstdielectric layer includes a first dielectric material; and the seconddielectric layer includes a second dielectric material different fromthe first dielectric material.
 4. The semiconductor device of claim 3,wherein the first and second dielectric materials include an oxide, anitride, an oxynitride, or a combination thereof.
 5. The semiconductordevice of claim 1, further comprising: one or more vias extending fromthe front side of the semiconductor substrate past the second dielectricmaterial on the back side, the one or more vias coupled with theintegrated circuit and configured to provide one or more electricalconnections for the integrated circuit on a surface of the seconddielectric material.
 6. The semiconductor device of claim 1, wherein thefirst and second dielectric layers share an interface vertically alignedwith the sidewall of the semicondutor device.
 7. A semiconductor device,comprising: an integrated circuit formed on a front side of asemiconductor substrate; a first dielectric layer on a back side of thesemiconductor substrate opposite to the front side; and a seconddielectric layer on a sidewall of the semiconductor substrate anddirectly contacting the first dielectric layer at a substantiallyvertical interface coplanar with the sidewall of the semiconductordevice.
 8. The semiconductor device of claim 7, wherein the seconddielectric layer is discontinuous from the first dielectric layer. 9.The semiconductor device of claim 7, wherein the second dielectric layerincludes at least two dielectric materials.
 10. The semiconductor deviceof claim 7, wherein: the first dielectric layer includes a firstdielectric material; and the second dielectric layer includes a seconddielectric material different from the first dielectric material. 11.The semiconductor device of claim 10, wherein the first and seconddielectric materials include an oxide, a nitride, an oxynitride, or acombination thereof.
 12. The semiconductor device of claim 7, furthercomprising: one or more vias extending from the front side of thesemiconductor substrate past the second dielectric material on the backside, the one or more vias coupled with the integrated circuit andconfigured to provide one or more electrical connections for theintegrated circuit on a surface of the second dielectric material.